ECOOP 2024
Mon 16 - Fri 20 September 2024 Vienna, Austria
co-located with ISSTA/ECOOP 2024
Wed 18 Sep 2024 11:30 - 11:45 at EI 2 Pichelmayer - Synthesis and verification Chair(s): Peter Thiemann

Synthetic Separation Logic (SSL) is a formalism that powers SuSLik, the state-of-the-art approach for the deductive synthesis of provably-correct programs in C-like languages that manipulate heap-based linked data structures. Despite its expressivity, SSL suffers from two shortcomings that hinder its utility. First, its main specification component, inductive predicates, only admits first-order definitions of data structure shapes, which leads to the proliferation of ``boiler-plate'' predicates for specifying common patterns. Second, SSL requires concrete definitions of data structures to synthesise programs that manipulate them, which results in the need to change a specification for a synthesis task every time changes are introduced into the layout of the involved structures.

We propose to significantly lift the level of abstraction used in writing Separation Logic specifications for synthesis — both simplifying the approach and making the specifications more usable and easy to read and follow. We avoid the need to repetitively re-state low-level representation details throughout the specifications — allowing the reuse of different implementations of the same data structure by abstracting away the details of a specific layout used in memory. Our novel high-level front-end language called Pika significantly improves the expressiveness of SuSLik.

We implemented a layout-agnostic synthesiser from Pika to SuSLik enabling push-button synthesis of C programs with in-place memory updates, along with the accompanying full proofs that they meet Separation Logic-style specifications, from high-level specifications that resemble ordinary functional programs. Our experiments show that our tool can produce C code that is comparable in its performance characteristics and is sometimes faster than Haskell.

Wed 18 Sep

Displayed time zone: Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna change

10:30 - 12:00
Synthesis and verificationTechnical Papers at EI 2 Pichelmayer
Chair(s): Peter Thiemann University of Freiburg, Germany
10:30
15m
Talk
Inductive Predicate Synthesis Modulo Programs
Technical Papers
Scott Wesley Dalhousie University, Maria Christakis TU Wien, Jorge A. Navas Certora, Richard Trefler University of Waterloo, Valentin Wüstholz ConsenSys, Arie Gurfinkel University of Waterloo
10:45
15m
Talk
Fearless Asynchronous Communications with Timed Multiparty Session Protocols
Technical Papers
Ping Hou University of Oxford, Nicolas Lagaillardie Imperial College London, Nobuko Yoshida University of Oxford
11:00
15m
Talk
Java Bytecode Normalization for Code Similarity Analysis
Technical Papers
Stefan Schott Heinz Nixdorf Institut, Paderborn University, Serena Elisa Ponta SAP Security Research, Wolfram Fischer SAP Security Research, Jonas Klauke Heinz Nixdorf Institut, Paderborn University, Eric Bodden Heinz Nixdorf Institut, Paderborn University and Fraunhofer IEM
11:30
15m
Talk
Higher-Order Specifications for Deductive Synthesis of Programs with Pointers
Technical Papers
David Young University of Kansas, USA, Ziyi Yang National University of Singapore, Ilya Sergey National University of Singapore, Alex Potanin Australian National University
11:45
15m
Talk
Matching Plans for Frame Inference in Compositional Reasoning
Technical Papers
Andreas Lööw Imperial College London, Daniele Nantes-Sobrinho Imperial College London, Sacha-Élie Ayoun Imperial College London, Petar Maksimović Imperial College London, UK, Philippa Gardner Imperial College London

Information for Participants
Wed 18 Sep 2024 10:30 - 12:00 at EI 2 Pichelmayer - Synthesis and verification Chair(s): Peter Thiemann
Info for room EI 2 Pichelmayer:

Map: https://tuw-maps.tuwien.ac.at/?q=CF0235

Room tech: https://raumkatalog.tiss.tuwien.ac.at/room/15717